AES加密算法在AP中的设计和实现  

The Design and Realization of AES Algorithm in AP

作　　者：夏劲伟[1] 高俊芳[2] 曹秀英[3] 吕俊怀[1] 

机构地区：[1]徐州师范大学计算机科学与技术学院,江苏徐州221116 [2]徐州师范大学图书馆,江苏徐州221116 [3]东南大学移动通信国家重点实验室,江苏南京210096

出　　处：《电子科技》2006年第12期39-44,共6页Electronic Science and Technology

摘　　要：随着无线局域网(WLAN)的发展,其信息的安全也越来越受重视。AES作为无线局域网通信协议的核心加密算法,如何用硬件实现并应用在通信产品中尤为重要。文中在概述了AES(高级加密标准)算法基本原理的基础上,以FPGA为硬件平台,Altera公司的QuartusII为工具,设计了AES加密算法在AP(AccessPoint)中的硬件实现。实现了AES加密解密电路的顺序循环方式和两级流水线方式设计,并对这两种实现方式进行了比较。结果表明采用流水线方式设计虽然增加了资源消耗,但是明显的提高了速度。With the development of WLAN, more attention is paid to information security. How to apply AES, a kernel encryption algorithm of WLAN communication protocols, in communication products with hardware realization is of great importance. Taking PFGA as hardware desktop and making use of Quartus II of Altera company as tools, the author designs hardware realization of AES encrypt algorithm in AP （Access Point） based on the algorithm principle theory of AES （Advanced Encryption Standard）. Two kinds of AES encryption and decryption circuit are designed： one being sequence cycle fashion, another being 2 stages of pipeline. This paper also compares them. Results indicate that using pipelining structure increases resource consumption but generally provides higher throughput.

关 键 词：AES FPGA 流水线 吞吐量 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程]