一种太比特路由器交换核心的研究与设计  

Research on and Design of a Novel Switch Core for Terabit Routers

作　　者：彭来献[1] 路欣[2] 赵文栋[1] 田畅[1] 

机构地区：[1]解放军理工大学通信工程学院,南京210007 [2]总参第63研究所,南京210007

出　　处：《电讯技术》2006年第6期122-127,共6页Telecommunication Engineering

摘　　要：硬件可扩展性和高效的性能一直以来是高速交换核心设计中的一对矛盾。文中在总结高速交换核心关键技术之后,提出了一种基于iRGRR算法的高速交换核心,它具有硬件实现简单、可扩展性强、性能优良等特点,大大缓解了上述矛盾。该交换核心能够提供服务质量保证,支持IP分组调度,可应用于太比特路由器中。文中还简要分析了该交换核心的性能,并给出了硬件设计方案。In the design of high - speed switch cores, there has existed a contradiction between scalability in hardware and efficient performance. After summarizing the key technologies of high - speed switch cores, a novel switch core based on iRGRR（ iterative request - grant - based round - robin） scheduling algorithm is presented. This switch core has many good features, such as simple, scalability and fine performance, and its appearance greatly relaxes the contradiction mentioned above. The switch core can also provide quality of service guarantees and support scheduling of IP packets, so it can be used in terabit routers. The performance of the switch core is also analysed, and hardware design scheme is given.

关 键 词：路由器 交换核心 输入排队 iRGRR算法 可扩展性 

分 类 号：TN915.05[电子电信—通信与信息系统]