基于FPGA的数字视频多窗口内存地址生成器设计  

Digital Video Multi-window Memory Address Generator Design Based on FPGA

作　　者：冯永茂[1] 徐秀知[1] 邓春健[1] 丁铁夫[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所

出　　处：《液晶与显示》2006年第6期708-713,共6页Chinese Journal of Liquid Crystals and Displays

基　　金：国家科技创新基金资助项目(No.020262112(0540))

摘　　要：通过变更地址计数器输出值到内存地址的映射关系,以最小的逻辑资源在单时钟周期内实现了数字视频处理中所需的内存地址偏移与跳变计算。阐述了该方法在数字视频并行处理中的基本应用、基本的设计与分析思路,以视频处理中常用到的逐行、逐列扫描方式为实例,介绍了行向窗口分布、列向窗口分布以及混合窗口分布的地址复换器的FPGA逻辑设计和仿真结果,并给出了地址映射变换关系的数学表达式。以基于FPGA的视频传输系统为实例,描述了多种地址生成器的设计方法与具体应用形式。This paper memory address ntroduces a method on how to use the relationship between the binary counter and the ng space, and designs a multi-window memory address generator to meet high efficiency data transmission requirement of the parallel digital video processing based on FPGA. With the smallest logical source occupying and no negtive effort to timing closure of the FPGA designing, the multi-window memory address generator can achieve many kinds of data exchange requirement even in the SDRAM operating environment. The logical design and MAX＋plus Ⅱ simulation results of some useful multi-window memory address generators are also introduced. These generators were designed to satisfy row oriented window splitting, colunm oriented window splitting, or row and column oriented multi window splitting with non interleaved scanning or column to column scanning method. As an instance, a kind of digital video transmission system based on FPGA and the fast ethernet PHYs, the detailed design methods and the address mapping table with their related mathematics expressions were all introduced.

关 键 词：数字视频处理 FPGA 地址映射 缓存操作 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]