基于CPLD高速可程控数字延迟线的设计与实现  

Design and Accomplishment of high-speed Programmable digital delay line system based on CPLD

作　　者：王群要[1] 高大庆[2] 上官靖斌[2] 黄志海[2] 辛俊业[2] 

机构地区：[1]北京市中科院研究生院,100080 [2]甘肃兰州市中科院近代物理研究所,730000

出　　处：《微计算机信息》2006年第12Z期134-136,231,共4页Control & Automation

摘　　要：针对兰州重离子加速器冷却储存环(HIRFL-CSR)踢轨磁铁(Kicker)电源的需要,设计了一种基于可编程逻辑器件(CPLD)的高速可程控数字延迟线系统。文中分析介绍了数字延迟线系统结构、工作原理及CPLD芯片的设计并给出了仿真波形。该方案满足了Kicker电源对脉冲进行适当延迟的要求,解决了Kicker电源系统脉冲同步的问题。To meet the need of kicker power supply of HIRFL-CSR, this paper designs a high-speed Programmable digital delay line system based on CPLD.h presents the circuit configuration the working principle and the CPLD design of digital delay line system with simulation figure. The design meets the need of kicker power supply of CSR to delay the pulse suitably, resolves the problem of the pulse in-phase of kicker power supply system.

关 键 词：CPLD 可程控 延迟线 Kicker 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]