基于NIOS II的中断技术在解算芯片的应用  

Application for Navigation Solution Chip of NIOS II-based Exception Handling Technology

作　　者：王春寒[1] 胡建萍[1] 胡正勇[1] 

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2006年第6期45-48,共4页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：浙江省科技厅重点计划项目(KYZ041104008)

摘　　要：大多数微处理器系统中都有一个中断系统及优先级逻辑。在NIOS II系统中也包含这些功能。NIOS II系统利用硬件抽象层系统库的应用程序接口函数创建中断服务子程序和管理寄存器窗口。该文主要分析了基于NIOS II的中断处理技术,并提供了导航解算芯片数据传输的解决方案,选择以FPGA作为导航解算芯片,结合配置芯片和接口芯片构建硬件系统,在NIOS II集成开发环境下开发应用程序,利用中断处理技术实现数据传输,并且满足数据信息传输和处理的精度和可靠性要求。A large number of microprocessors have interrupt system and priority logic. NIOSⅡ also includes these functions. NIOSⅡ system includes some subprograms that easy to implement ISR. The HAL system library provides an API to help ease the creation and maintenance of ISR. This paper mainly analyses NIOSⅡ - based exception handling technology, and provides a solution of navigation solution chip. The solution selects FPGA as navigation solution chip, constructs hardware system with configuration chip and interface chip, develops application program in NIOSⅡ integrated development environment, takes use of exception handling technology to transmit data, and satisfies accuracy and reliability of transmission and handler of digit information.

关 键 词：中断技术 解算 接口芯片 

分 类 号：TN368.1[电子电信—物理电子学]