基本数字时序电路Spice宏模型的建立  

Building the Basic Digital Sequence Circuit Macro-Model in Spice

作　　者：沈磊[1] 

机构地区：[1]电子科技大学,成都610054

出　　处：《实验科学与技术》2006年第B12期12-14,共3页Experiment Science and Technology

摘　　要：提出了在SPICE中建立数字时序电路宏模型的新方法。模型主要由受控源搭建而成,结构简单、仿真速度快,并且精度高,在SPICE仿真中大量用到,有良好的应用价值。文中主要讨论常用时序逻辑模型(D锁存器、D触发器和T触发器)的建立。A new method of developing digital sequence circuit macro - models in SPICE is proposed in this article. The macro- models are mainly made up of the controlled sources and passive components. This article mainly discusses the building of such sequence logic models as D_ latch, D_FF and T_FF.

关 键 词：宏模型 数字电路模型 SPICE模型 时序电路模型 

分 类 号：TN431.2[电子电信—微电子学与固体电子学] TP391.9[自动化与计算机技术—计算机应用技术]