基于计算机并口的时序模拟及其在单片机ISP中的应用  

The Timing Sequence Simulation and Its Application to SCM ISP Based on Parallel Port of Computer

作　　者：杜敬仓[1] 史小军[1] 

机构地区：[1]东南大学电子工程系,江苏省南京市210096

出　　处：《电子工程师》2007年第1期55-57,共3页Electronic Engineer

摘　　要：计算机并口主要用来连接打印机,由于数据并行传输,所以传输速度相对较快。文中介绍了如何在VC++.NET下,通过动态链接库W inIo对并口进行操作来模拟典型的总线时序。ATMEL的AT89S52单片机具有8 kB的Flash程序存储器,支持ISP(在系统下载),可以方便地升级程序。The parallel port of computer is mainly used for connecting to printer, the data transmission rate is rapid because the data is transferred in parallel. This article introduces how to control the parallel port in the VC＋＋ . NET through DLL Winlo, to control the parallel port to simulate the bus timing sequence. The AT89S52 has 8 kB flash memory which can be programmed to upgrade the system conveniently.

关 键 词：并口 时序模拟 ISP WinIo 单片机 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构]