基于频谱平均法的ADC模块性能评估  

Performance Evaluation of ADC Blocks Based on the Spectrum Averaging Method

作　　者：杨一鸣[1] 吴曼青[1] 郑生华[2] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽省合肥市230009 [2]华东电子工程研究所,安徽省合肥市230031

出　　处：《电子工程师》2007年第1期58-60,共3页Electronic Engineer

摘　　要：采用频谱平均法分析时钟抖动和加性白噪声对ADC(A/D转换器)模块噪声基底的影响,推导出噪声基底的数学公式,并通过仿真验证了其正确性。结合公式,改变信号频率或采样频率进行采样,绘出相应的噪声基底频谱,观测噪声基底的变化,可以推断出时钟抖动和加性白噪声的影响,借此评价采样保持电路和外围电路的性能,决定是否要对其进行改进。仿真分析表明,这是一种评估ADC系统性能的好方法,为其改进提供了理论支持。This paper adopts the spectrum averaging method to analyze the effects of clock jitter and the additive white noise to the noise floor of ADC blocks, and derives the noise floor formula, which is validated by computer simulation. Using the formula, and plotting the graphs of noise floor as the function of the signal frequency or sampling frequency, the changes of the noise floor can be observed, from which the effects of clock jitter and the additive white noise can be deduced. Then the performances of the sample/hold circuit and the peripheral circuit are evaluated, so that the decision of whether to improve them can be made. The simulations indicate that this is a good method to evaluate the system performance of ADC and provides a theoretical support for its improving.

关 键 词：A/D转换器 频谱平均 噪声基底 

分 类 号：TP335.1[自动化与计算机技术—计算机系统结构]