一种通用的可编程双模分频器(英文)  

A Generic Programmable Dual Modulus Divider

作　　者：黄水龙[1] 王志华[2] 

机构地区：[1]清华大学电子工程系,北京100084 [2]清华大学深圳研究生院,深圳518055

出　　处：《北京大学学报（自然科学版）》2007年第1期109-112,共4页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：国家高技术研究发展计划(60475018);国家重点基础研究发展规划(G2000036508)资助项目

摘　　要：提出了一种通用的可编程双模分频器,电路主要由3部分组成9/8预分频器,8位可编程计数器和ΣΔ调制器构成。通过打开或者关断ΣΔ调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能。9/8预分频器采用提高的TSPC动态触发器实现,而可编程分频器和调制器采用数字综合后布局布线的方法实现。基于SMIC0.18μm1.8V电源CMOS工艺的SpectreVerilog仿真表明它能在分频比56-2047范围内工作,最大工作频率大于2GHz,消耗的电流小于4mA,适合应用在高性能的频率综合器中。A programmable dual modulus divider is proposed. The circuit mainly includes three building blocks： prescaler, 8-bit programmable counter and ∑△ modulator. Two operation modes （integer/fractional-N） are achieved by switching on/off the output signal of the ∑△ modulator. Only a programmable counter is needed for the swallow pulse divider. The prescaler was designed by using the improved dynamic TSPC triggers, and the other blocks were realized by the way of digital synthesis, placing and routing. Based on 0.18 μm 1.8 V CMOS technology, SpectreVerilog simulations verify that it can operate within the division ratio of 56- 2 047 with 2 GHz maximum operation frequency and 〈 4 mA current dissipation. The circuit is very simple and can be used in the high performance PLL frequency synthesizer.

关 键 词：分频器 ∑△调制器 计数器 三线接口 

分 类 号：TN772[电子电信—电路与系统]