二维5/3小波变换的结构设计与FPGA实现  

Architecture and FPGA-Based Implementation of 2-D 5/3 Discrete Wavelet Transform

作　　者：王承君[1] 熊承义[1] 

机构地区：[1]中南民族大学电子信息工程学院,武汉430074

出　　处：《中南民族大学学报（自然科学版）》2006年第4期50-53,共4页Journal of South-Central University for Nationalities：Natural Science Edition

基　　金：湖北省自然科学基金资助项目(2006ABA370)

摘　　要：给出了一种二维5/3小波变换的结构设计与FPGA实现的方法.采用提升的方法完成了一维结构的设计,能够有效地提高系统的数据处理能力.二维结构采用直接的行列分离变换方式,通过增加一个较小的内部RAM单元有效减少系统的控制复杂度.用可综合的V erilog硬件描述语言完成了对设计的描述,并在Q uartus II软件下进行了功能仿真和逻辑综合,以及综合后的时序仿真.通过硬件仿真结果与采用M atlab的软件仿真结果验证了设计的正确性.实验结果表明:该设计方案具有控制简单和较低的硬件资源需求的优点.An effective architecture design and Hardware implementation using FPGA for 2-D 5/3 wavelet transform is investigated. One-D architecture can improve the data process capacity when the lifting scheme is adopted. With an additional small RAM, the control complexity of 2-D architecture can be efficiently reduced. Verilog HDL models for all the designs are described, which have been synthesized, simulated and configured into FPGA chip using integration software tool Quartus Ⅱ. We have validated the design by comparing the results of hardware simulation with that of MATLAB simulation. The experimental results show that the design has the advantages of simplicity of control logic and low hardware cost.

关 键 词：小波变换 提升算法 现场可编程门阵列 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]