Turbo译码器的改进算法及FPGA实现  

Improved decoding algorithm and FPGA-based implementation of Turbo coder

作　　者：于秀兰[1] 冉静 

机构地区：[1]重庆邮电学院,重庆400065 [2]北京大唐集团,北京100038

出　　处：《计算机工程与应用》2007年第3期93-95,共3页Computer Engineering and Applications

基　　金：重庆邮电学院青年创新基金项目。

摘　　要：在传统的Turbo译码算法Log-MAP的基础上,对译码算法和SISO译码模块进行了优化,得到了改进的SW-Log-MAP算法,它在保证译码性能的前提下,大大降低了其运算复杂度,减少了存储空间。并且给出了改进译码算法硬件实现的设计方案,完成了Turbo译码器的FPGA实现,通过测试证明,译码器达到了设计要求。Derived from the conventional Log-MAP decoding algorithm of Turbo code and based on the decoding algorithm and the soft-input soft-output （SISO） decoding module,the improyed SW-Log-MAP algorithm is put forward.Based on simulation,the conclusion is drawn that computational complexity and storage requirement are reduced with no performance degradation.Also,the FPGA-based design of the improved Turbo decoder and implementation of the decoder are finished,which meets the requirement of the design through testing.

关 键 词：TURBO码 迭代译码算法 改进的SW—Log—MAP算法 FPGA 

分 类 号：TN912.3[电子电信—通信与信息系统]