12位60MS/s采样保持电路的设计  

Designing of a 12-bit 60MS/s sample-and-hold circuit

作　　者：刘睿强[1] 景新幸[1] 王晓晖[1] 

机构地区：[1]桂林电子科技大学信息与通信学院ASIC研究室,广西桂林541004

出　　处：《桂林电子科技大学学报》2007年第1期14-18,共5页Journal of Guilin University of Electronic Technology

摘　　要：通过增益提升电路,使用于高速高分辨率ADC中的CMOS全差分采样保持电路,能达到高增益高带宽。利用电容下级板采样技术和自举开关消除电荷注入,以全差分结构抑制噪声来提高线性度,使采样精度达到了0.012%.经过Cadence软件Hspice平台仿真,在3.3V电源电压下,用TSMC0.20umCMOS工艺模型,在驱动2PF负载时,直流增益可达112DB,相位裕度为69.7度,单位增益带宽为547.2MHz,压摆率463V/us,功耗19.1 mW.This paper first discusses using a gain-boosted circuit to design a CMOS fully differential sample-and- hold circuit which is used in the high-speed and high-resolving ADC. The design objective of high dc gain and GBW is obtained. The charge injection is removed through the capacitance subordinate sample technique and boosted switch and the linearity and noise suppression are increased through the fully-differential structure. 3.3 V power supply and TSMC 0. 35urn CMOS process technology are used to achieve the dc open-loop gain of 112 dB with 547.2MHz unity gain bandwidth, 65 phase margin, 463V/us slew rate and 19.1 mW power consumption.

关 键 词：采样保持 CMOS运算放大器 增益提升 自举开关 

分 类 号：TN432[电子电信—微电子学与固体电子学]