采用数据流模式提高乱序执行密码芯片的安全性  

Improve the Security of Random Executing Encryption ICs by the Data Flow Mode

作　　者：李翔宇[1] 孙义和[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《电子学报》2007年第2期202-206,共5页Acta Electronica Sinica

基　　金：国家自然科学基金重点基金项目(No.60236020);高等学校博士学科点专项科研基金(No.20050003083)

摘　　要：乱序执行是密码芯片设计中一种低冗余、低功耗的抵抗功耗分析攻击的方法.芯片安全性随着操作执行时刻不确定度的增加而提高.基于数据流模式的乱序执行AES加密集成电路采用动态数据流结构、对并发操作串行地随机服务,通过增加顺序无关操作的数量和成批处理令牌提高不确定度.其中采用了新的令牌暂存-匹配-发射结构完成令牌的同步和对随机执行的控制.实验芯片的所有操作均实现了不确定执行,可以抵抗样本数小于15000的相关功耗分析攻击,芯片功耗低于所知的其它抗功耗分析攻击AES芯片.The random order execution which used in cryptographic ICs is a kind of few redundancy and low power countermeasures against power analysis attacks. The security is stronger with higher degree of uncertainty of timing. A data flow random executing AES encryption ASIC adopted the dynamic data flow architecture and served concurrent tokens randomly and sequentially. Its uncertainty was enhanced by increasing the number of order independent operations and batch arrival of tokens. A novel token hold - match - fetch structure was designed to complete the synchronization and random service control. Finally, all of the operations were random executing. That chip can resist 15,000 samples Correlation Power Analysis. Its energy consumption is less than the known AES circuits with other

关 键 词：数据安全 集成电路设计 功耗分析攻击 

分 类 号：TP309.2[自动化与计算机技术—计算机系统结构] TN402[自动化与计算机技术—计算机科学与技术]