“龙腾”R2微处理器存储管理单元的设计与实现  

Second Generation Design of NWPU 32-bit RISC MMU(Memory Management Unit)

作　　者：屈文新[1] 樊晓桠[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《西北工业大学学报》2007年第1期137-141,共5页Journal of Northwestern Polytechnical University

基　　金：国家自然科学基金(60573143);西北工业大学研究生创业种子基金(200647)资助

摘　　要：虚拟内存是一种管理物理内存资源的技术,将虚拟地址空间映像到物理地址空间。提出了一种设计32位超标量微处理器存储管理单元体系结构的方法,实现了访存和访I/O的逻辑地址到物理地址的转换,讨论了TLB(Translation Lookaside Buffer)设计中的关键技术以及在段、块或页的基础上提供的访问保护,满足了“龙腾”R2微处理器芯片的设计要求。整个芯片采用0.18μmCMOS工艺实现,芯片面积在4.8 mm×5.2 mm之内,核心频率超过233 MHz,功耗小于1.5 W。In September, 2006, the Aviation Microelectronic Center of NWPU （Northwestern Polytechnical University ） completed the development of the second generation NWPU 32-bit super-scalar RISC microprocessor, which we call ＂Longtium＂ R2. In this paper we present the design of the MMU of ＂Longtium＂ R2, which we deem to be successful because this MMU helps ＂Longtium＂ R2 to meet performance requirements. In section 2, we explain block-address translation and page-address translation. Figs. I and 2 show respectively the block-address translation flow and page-address translation flow. As the most important logic in the whole design of MMU, the design of Translation Lookaside Buffer （TLB） is explained in detail in section 3; essentially, the design of TLB stresses the reduction of the area of the chip and making the speed of chip high. Section 4 analyzes respectively the mechanisms of memory protection and exception processing. Section 5 gives the synthesis results of simulation in Tables 4 and 5 and these results show that design objectives are attained. Section 6 summarizes that the ＂Longtium＂R2 CPU is fabricated in a 0.18μm CMOS process, the die size of the chip is within 4. 8 min×5.2 mm and the CPU operating frequency is at least 233MHz.

关 键 词：存储管理单元 逻辑地址 物理地址 TLB 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]