一种用于高速高精度A/D转换器的自举采样电路  

A Bootstrapped Sampling Circuit for High-Resolution and High-Speed A/D Converter

作　　者：王磊[1] 尹文婧[1] 许俊[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学》2007年第1期80-84,共5页Microelectronics

基　　金：上海市科委集成电路设计专项重点项目"低电压;低功耗;流水线CMOS高速模数转换器"资助(47062005)

摘　　要：介绍了一种新型的CMOS自举采样电路。该电路适用于12位100 MHz采样频率的A/D转换器。采用P型栅压自举开关补偿技术,可以有效地克服采样管导通电阻变化引入的非线性失真,提高采样精度。仿真结果表明,采样时钟频率为100 MHz时,输入10 MHz信号,可得信噪失真比(SNDR)为102 dB,无杂散动态范围(SFDR)为103 dB。信号频率达到采样频率时,仍有超过85 dB的SNDR和87 dB的SFDR,满足高速高精度流水线A/D转换器对采样开关线性度和输入带宽的要求。电路采用SMIC 0.18μm CMOS数模混合工艺库实现,电源电压为1.8 V。A novel CMOS bootstrapped sampling circuit for 12-bit, 100 MS/s pipelined A/D converter is presented. By compensating with P-type bootstrapped switch, this circuit can overcome nonlinear distortion, which is generally introduced by signal-dependent on-resistance, and improve sampling resolution. Implemented in SMIC＇s 0. 18 μm CMOS mixed signal technology, the circuit operates from a 1.8 V power supply. At a 100 MHz sampling clock frequency and 10 MHz input signal, signal-to-noise-and-distortion ratio （SNDR） and spurious-free dynamic range （SFDR） goes to 102 dB and 103 dB respectively. It maintains both SNDR and SFDR over 85 dB for input frequencies up to the sampling frequency, which satisfies the requirement of S/H circuit in high-resolution and high-speed pipelined A/D converter.

关 键 词：模数转换器 CMOS开关 自举采样 信噪失真比 无杂散动态范围 非线性失真 

分 类 号：TN432[电子电信—微电子学与固体电子学]