适用于HDTV的低抖动时钟电路  

A Low-Jitter Clock Generator for HDTV

作　　者：陈丹凤[1] 陆平[1] 李联[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学》2007年第1期147-150,共4页Microelectronics

基　　金：上海市经委"数字电视地面传输芯片"资助项目;上海市信息委"高清晰数字电视地面传输芯片设计"资助项目

摘　　要：采用高速鉴频鉴相器、抗抖动电荷泵和差分对称负载延迟单元优化结构,综合分析环形振荡器各类噪声模型,设计了一种适用于HDTV的低抖动时钟电路。芯片采用SMIC 0.35μm标准CMOS工艺,3.3 V电源电压。在一定测试环境下,输出30 MHz时钟信号抖动σ仅为10.4 ps,能很好地满足电路设计要求。A low-jitter clock generator for HDTV is designed with a high-speed phase/frequency detector, a noise-suppressed charge pump and symmetrical load differential delay cells. Different noise models of the ring oscillator are discussed. Implemented in SMIC＇s 0. 35μm standard CMOS process, the circuit operates at 3, 3 V power supply. Under certain testing circumstance, clock jitter of the voltage controlled oscillator for 30 MHz output is 10.4 ps, which meets the specification well.

关 键 词：时钟抖动 频率综合器 压控振荡器 相位噪声 高清电视 

分 类 号：TN431[电子电信—微电子学与固体电子学]