低压高速LDO电路系统的分析与设计  

Analysis and Deign of High Speed LDO Circuits

作　　者：黄晶生[1] 吴金[1] 刘凡[1] 姚建楠[1] 

机构地区：[1]东南大学无锡分校,江苏无锡214028

出　　处：《电子器件》2007年第1期259-262,共4页Chinese Journal of Electron Devices

基　　金：无锡市自然科学基金资助项目(CK040005)

摘　　要：在基本LDO电路结构及其频率特性分析的基础上,分析了常规LDO电路动态特性局限产生的根源,并重点讨论了基于NMCNR、AFFC及自适应偏置三种运放结构大电流负载驱动的高速LDO电路设计,分析、比较了不同补偿方式对系统动态性能和稳定性的影响.采用CSMC0.6μmCMOS工艺,通过Hspice完成了电路性能的模拟,实际结果验证了电路在负载瞬态调节性能上的明显改善和提高.Based on the analysis of generic Low-Dropout Circuit and its frequency response, the dynamic performance restriction of LDO was analyzed. And, three kinds of larger current driving LDO circuits consist of NMCNR, AFFC and self-biased OP are presented on emphases and the influence of different compensation on system dynamic performance and stability are analyzed and compared. The simulation results are obtained by Hspice based on CSMC 0. 6 μm CMOS process, which indicated that the clearly improvement in transient response has been realized in the system.

关 键 词：LEX9 频率补偿 HSPICE 瞬态响应 

分 类 号：TN402[电子电信—微电子学与固体电子学]