并口JTAG仿真器的设计与实现  

Design and Implementation of Parallel Port JTAG Emulator

作　　者：许建荣[1] 姚国良[1] 胡晨[1] 

机构地区：[1]东南大学电子工程系国家专用集成电路系统工程中心,南京210096

出　　处：《电子器件》2007年第1期314-317,共4页Chinese Journal of Electron Devices

摘　　要：通过对JTAG协议和标准并口规范的研究,提出了适合嵌入式系统调试的并口JTAG仿真器的实现方案.给出了硬件电路的设计,并通过并口信号的软件时序模拟实现底层通信从而完成JTAG协议的转换,最后提出开放接口的驱动软件架构,可以对目标机器进行在线编程和调试,实现人机交互以及与第三方开发工具的交互,并对基本功能进行了验证.Based on the research of the standard of JTAG and parallel port, a scheme for design of parallel port JTAG emulator that is used in debugging of embedded system is proposed. This scheme includes the hardware schematic and the communication between JTAG and parallel port by programming the related pins according to the JTAG communication protocol. The architecture of software driver for the open interface is also provided so that the developer and the third-part software can interact with the emulator for in-system programming and debug. Experimental results show that this design is effective.

关 键 词：嵌入式系统 调试 仿真器 并口 JTAG 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]