CIRCUIT TESTABLE DESIGN AND UNIVERSAL TEST SETS FOR MULTIPLE-VALUED LOGIC FUNCTIONS  

作　　者：Pan Zhongliang 

机构地区：[1]School of Physics and Telecommunication Engineering, South China Normal University, Guangzhou 510631, China

出　　处：《Journal of Electronics(China)》2007年第1期138-144,共7页电子科学学刊（英文版）

基　　金：Supported by the National Natural Science Foundation of China (No.60006002);the Education Department of Guangdong Province of China (No.02019).

摘　　要：The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n＋1 vectors detect all skew faults in the circuit realization of multiplevalued functions with n inputs. Secondly, min（max） bridging fault test sets with n＋2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiplevalued logic functions.

关 键 词：Multiple-valued logic Testable realization Single faults Bridging faults Skew faults. 

分 类 号：TN710[电子电信—电路与系统]