一种改进的高性能全差分电荷泵设计  

Design of an Improved High Performance Differential Charge Pump

作　　者：黄水龙[1] 王志华[1] 

机构地区：[1]清华大学电子工程系

出　　处：《电子器件》2006年第4期1053-1057,共5页Chinese Journal of Electron Devices

基　　金：国家高技术研究发展计划资助项目(60475018);国家重点基础研究发展规划的部分支持(G2000036508)

摘　　要：简要讨论了电荷泵中的非线性问题及常用的一些结构,提出了一种改进的基于负反馈的全差分电荷泵结构。它由充电/放电模块,共模反馈电路以及偏置电路组成。负反馈结构使得输入能有效跟踪输出,实现高的上下电流匹配;而共模反馈通过稳定输出静态工作点来抑制差分输出线上的共模扰动。为了测试电荷泵对锁相环路的影响,基于0.25μm 2.5 VCMOS工艺实现了一个电荷泵原型,并用verilogA对锁相环路的其它模块建模。仿真和计算表明:在0.3 V到2.3 V的电压范围内,电流静态失配小于0.01%,在100 kHz环路带宽下,能获得<-75 dBc的杂散电平,适合应用在高性能的锁相环中。The nonlinearities and some general structures of charge pump are briefly discussed in the paper. An improved differential charge pump based on negative feedback is then presented. It comprises two charge/discharge blocks, a common-mode feedback （CMFB） block and a bias circuit. The negative feedback circuit makes the input effectively track the output, achieving a high up/down current matching regardless of output voltage. The CMFB circuit is utilized to reduce the common-mode disturbance of differential output lines by stabilizing the static operation solution. In order to test charge pump＇s influence in a PLL, a charge pump prototype is implemented using a 0. 25 um 2. 5 V CMOS technology, and the other blocks in PLL loop are modeled based on verilogA language. Simulation and calculation shows that the charge pump has a 〈0. 01% mismatching in 0. 3-2.3 V range, and a 〈-75 dBc spur level in a 100 kHz loop bandwidth, which is suitable for high performance PLL.

关 键 词：电荷泵 锁相环 杂散信号 

分 类 号：TN702[电子电信—电路与系统]