低翻转率的SoC总线组合编码算法  

Combination Encoding Algorithm of Low Transition on SoC Bus

作　　者：胡国兴[1] 沈海斌[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,杭州310027

出　　处：《电子器件》2006年第4期1239-1241,1245,共4页Chinese Journal of Electron Devices

基　　金：国家863计划资助项目(2003AA141050;2003AA1Z1060)

摘　　要：为降低SoC总线功耗,避开现有总线编码技术在应用上的局限,提出了一种SoC总线编码算法。算法基于总线上IP可复用的观点,采用分组BI码和T0码各自的优点,在维持SoC总线功能基本不变的同时,减少数据线和地址线的电平翻转。最后的实验结果表明:组合编码算法可以将SoC总线的平均功耗下降7.41%,是一种有效且适用于SoC总线的低功耗算法。To lower power dissipation of SoC bus and to keep away from the limitation of existing bus enco- ding technology in application field, an algorithm based on combination encoding is proposed. Taking account of maintaining SoC Bus function, decomposition bus-invert coding and zero-transition coding are all adopted to decrease transition rates of data lines and address lines. The algorithm significantly reduces 7. 41% power dissipation of chip-on bus. Results show that it＇s both effective and feasible for SoC bus.

关 键 词：翻转率 功耗 总线 片上系统(SOC) 

分 类 号：TN919.3[电子电信—通信与信息系统]