一种用于分数频率合成器的3阶单环ΣΔ调制器  

A 3rd Order Single Loop ΣΔ Modulator in Fractional-N Frequency Synthesizer

作　　者：胡康敏[1] 沈维伦[1] 黄煜梅[1] 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《固体电子学研究与进展》2007年第1期74-78,共5页Research & Progress of SSE

摘　　要：分析了无线通信分数分频频率合成器的关键模块ΣΔ调制器(SDM)的设计方法,并提出了一种系数能用移位产生的简单高效的单环3阶3位量化SDM结构。该电路采用标准0.18μm CM O S工艺实现,电源电压1.8 V,内部使用24位总线,在工作频率为16MH z时,可到达的频率分辨率为8 H z,结果表明它的带外噪声平坦、输出位宽窄,优于同阶级联ΣΔ结构。This paper analyzes the design methodology of ∑△ modulator（SDM） used in fractional-N frequency synthesizer for wireless communication, and an efficient and uncomplicated single loop 3^rd order 3-bit SDM is proposed. The circuit has been implemented in standard 0. 18 μm CMOS process. By using 24 bits bus, the frequency resolution of the SDM is 8 Hz when it operates at 16 MHz. A detailed analysis of it shows the flat out-of-band noise, narrow output bit pattern, and its performance are better than multistage ∑△ modulator with the same order.

关 键 词：∑△调制器 分数分频频率合成器 锁相环 

分 类 号：TN432[电子电信—微电子学与固体电子学]