Low Power Embedded Multimedia Processor Architecture  

作　　者：WEN Shuhong CUI Huijuan TANG Kun 

机构地区：[1]Department of Electronic Engineering, Tsinghua University, Beijing 100084, China [2]Information Engineering School, Communication University of China, Beijing 100024, China

出　　处：《Chinese Journal of Electronics》2007年第1期123-126,共4页电子学报（英文版）

基　　金：This work is supported by the National Natural Science Foundation of China （No.60272020）.

摘　　要：High performance and low power is critical to a handheld multimedia application. A low power embedded multimedia processor architecture is proposed： a 128-byte instruction loop buffer with special loop instruction, instruction cache/scratchpad memory, data scratchpad memory, multiple-bus architecture with one internal program bus and several internal data buses, unified program/data memory architecture, big-endian operation mode. Such DMA controller is very important for image and video encoding： a DMA transfer complete event can trigger another DMA transfer without CPU intervention, and single event can transfer a group of frames with inconsecutive elements.

关 键 词：Multimedia processor Loop buffer Scratchpad memory. 

分 类 号：TP37[自动化与计算机技术—计算机系统结构]