流水线结构FFT/IFFT处理器的设计与实现  

Design and Implementation of a Pipelined FFT/IFFT Processor

作　　者：何星[1] 张铁军[1] 侯朝焕[1] 

机构地区：[1]中国科学院声学研究所

出　　处：《微电子学与计算机》2007年第4期141-143,147,共4页Microelectronics & Computer

摘　　要：针对实时高速信号处理的要求,设计并实现了一种高效的FFT处理器。在分析了FFT算法的复杂度和硬件实现结构的基础上,处理器采用了按频率抽取的基-4算法,分级流水线以及定点运算结构。可以根据要求设置成4P点的FFT或IFFT。处理器可以对多个输入序列进行连续的FFT运算,消除了数据的输入输出对延时的影响,平均每完成一次N点FFT运算仅需要N个时钟周期。整个设计基于Verilog HDL语言进行模块化设计,并在Altera公司的CycloneII器件上实现。An efficient FFT processor is designed to meet the demand of real time and high speed signal processing. Based on the analysis of the complexity and hardware architecture of FFT, the proposed processor adopts radix-4 DIF algorithm, pipelined architecture and fixed-point operation. The processor can be configured as 4e-point FFT or IFFT, and can process FFT operations continuously by eliminating delay impact caused by data in/out and finish an N-point FFT computation in N clock cycles. The entire design is described in Verilog HDL language and implemented on the Cyclone Ⅱ device.

关 键 词：FFT 流水线 基—4 蝶形运算 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]