三层以太网交换机CPU收发包相关问题分析  

Analysis of Packet Sending and Receiving by L3 Ethernet Switch CPU

作　　者：赵振宁[1] 范力涵[1] 陈晓[1] 

机构地区：[1]中兴通讯股份有限公司,江苏南京210012

出　　处：《中兴通讯技术》2007年第2期47-49,共3页ZTE Technology Journal

摘　　要：三层以太网交换机发展迅速,一方面网络设备的带宽及交换容量大幅提升,另一方面设备所支持的协议种类也随着用户的需求不断增加。如何在大业务量的网络环境下确保各设备之间协议包的正常交互,是以太网交换机设计面临的重要问题。文章以基于ASIC的三层以太网交换机为例,从CPU负载、软硬件队列配置、CPU和交换芯片的通信机制等方面入手,讨论并分析在多进程环境中与CPU收发包功能相关的一些典型问题,得到解决办法。解决方法对于网络处理器(NP)同样适用。The L3 Ethernet switch has developed rapidly. On one hand, it has greatly improved bandwidth and exchange capability of network equipment. On the other hand, network equipment is required to support more protocol types with the increasing of user demands. For design of an Ethernet switch, it is important to ensure normal interaction of protocol packets between different devices under a network environment of massive traffic. Taking the L3 Ethernet switch that uses Application Specific Integrated Circuits （ASIC） chip as an example, this article analyzes several typical issues about packet receiving and sending by CPU under a multi-progress environment, including CPU load, software and hardware queue settings, and communication mechanism between CPU and the switching chip. It then gives solutions to these issues, which may also work for the Network Processor （NP）.

关 键 词：三层以太网交换机 CPU 中断 轮询 直接存储器存取 队列调度 

分 类 号：TN915.02[电子电信—通信与信息系统]