双蝶形高速脉冲压缩的FPGA实现  

Pulse Compression Based on FPGA Using Two Butterflies

作　　者：王超[1] 田黎育[1] 高梅国[1] 

机构地区：[1]北京理工大学信息科学技术学院,北京100081

出　　处：《数据采集与处理》2006年第B12期11-14,共4页Journal of Data Acquisition and Processing

摘　　要：在对脉冲压缩原理分析的基础上提出了适应于FPGA实现的结构,采用了数据全并行基4双蝶形单元计算结构,极大地提高了蝶形运算的并行度,从而提高了脉冲压缩的速度。设计了合理的数据流程,以较小代价实现了和差两路数据的脉冲压缩。根据二相码的特点采用了奇偶点分开并行脉冲压缩方法保证了脉压的效果和速度。在系统时钟100 MHz时,完成4 K点的脉冲压缩只需67μs。A novel digital pulse compression algorithm based on field programmable gate array （FPGA） is proposed, and two radix-4 butterflies are used in the algorithm. Parallel memory accessing for the decimation-in-time radix-4 FFT algorithm is discussed based on the ＂inplace＂ principle. And two radix-4 butterflies are calculated at the same time. Two digital pulse compression （DPC） modules are used to accomplish DPC of the odd number and the even number at the same time. Results show that a complex 4 K point pulse compression is caluclated about 67 μs at 100 MHz. Experiments show that the algorithm is feasible.

关 键 词：脉冲压缩 二相码信号 FPGA 

分 类 号：TN95[电子电信—信号与信息处理]