高速64点FFT芯片设计技术  

Implementation Technology of a High-speed 64-point FFT Chip

作　　者：赵梅[1] 丁晓磊[1] 朱恩[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏省南京市210096

出　　处：《电子工程师》2007年第3期13-17,共5页Electronic Engineer

摘　　要：针对高速64点FFT(快速傅里叶变换)处理芯片的实现,分析了FFT运算原理,并根据FFT算法原理介绍了改进的FFT运算流图。介绍了FFT处理器系统的各模块的功能划分,并根据FFT处理器结构及其特殊寻址方式,采用Verilog HDL对处理器系统的控制器、双数据缓存、地址生成器、蝶形运算单元以及I/O控制等模块进行了RTL(寄存器传输级)设计,并在ModelSim中对各模块以及整个系统进行功能仿真和验证,给出了部分关键模块的仿真波形图。设计中,注重从硬件实现以及电路的可综合性等角度进行RTL电路设计,以确保得到与期望性能相符的硬件电路。This paper introduces the implementation of a high-speed 64-point FFF （Fast Fourier Transform） chip. The FFF principle is presented at first. And then, based on the theory and principle of FFF algorithm, this paper analyzes an improved FFF operation flow chart. Then the architecture of the FFT operating system and the functions of each module are introduced. The FFT processor consists of a group of memories, address generating units, butterfly processing units, a system controller and an I/O controller. All these modules are described in Verilog HDL and each module is simulated in ModelSim successfully. The design of these primary modules is introduced taking the characteristics of FFF operation into account. The RTL level design focuses great attention on the hardware implementation and the synthesizability in order to obtain a circuit with the expected performance.

关 键 词：FFT(快速傅里叶变换) 蝶形运算单元 地址生成器 控制器 流水线 并行结构 

分 类 号：TN47[电子电信—微电子学与固体电子学]