基于ME算法的RS译码器的原理和FPGA实现  

Principles and FPGA Implementation of RS Decoder Based on ME Algorithm

作　　者：曾德才[1] 魏廷存 

机构地区：[1]西北工业大学软件与微电子学院,西安710065 [2]航空微电子中心,西安710072

出　　处：《科学技术与工程》2007年第9期1886-1889,共4页Science Technology and Engineering

摘　　要：RS(Reed-Solomon)码是具有很强纠错能力的线性分组码,广泛应用于各种通信和存储系统中。文中设计的译码器采用修正的欧几里德算法(MEA),并在实现中采用公共项提取算法有效地优化了乘法器,以迭代、复用等方法降低了RS码译码硬件实现的复杂度。并用Verilog-HDL语言实现了RS(255,239)码的译码器各个模块的功能。RS （Reed-Solomon） code is a linear block code having very strong capability of correcting random and burst errors, which is widely used in various communication and memory systems. In this paper, the decoder is designed using modified Euclidean algorithm （MEA）, the public extraction algorithm is used to optimize the multiplier, and the complexity and the power consumption of RS decoder are reduced by using the iteration and multiple methods. The all blocks of RS （255, 239） decoder are realized by Verilog-HDL.

关 键 词：Reed—Solomon译码 ME算法 FPGA Verilog—HDL 

分 类 号：TN919.3[电子电信—通信与信息系统]