CPLD在PWM电路设计中的应用  

Application of CPLD in PWM Circuit Design

作　　者：田玉利[1] 高伟[1] 宋宗玺[1] 

机构地区：[1]中国科学院西安光学精密机械研究所

出　　处：《科学技术与工程》2007年第9期2060-2063,2068,共5页Science Technology and Engineering

摘　　要：针对以往的用CPLD来设计PWM时存在的对死区时间的错误理解,介绍了一种基于复杂可编程逻辑器件(CPLD)的工程适用脉冲宽度调制(PWM)电路设计,源代码用VHDL语言编写,该电路能根据十六位输入数据产生精确的占空比可调的PWM信号,具有死区时间可调、接口简单、资源耗费少、精度高等优点。The way to design PWM circuit based on CPLD, the program is written by VHDL which is a hardware design language. This design can produce accurate PWM signal, according to 16 bits input, whose dead time can be regulate, interface is sample, consumption of resource is little and accuracy is high. It can be used in brushless DC Motor controlling.

关 键 词：CPLD 脉冲宽度调制(PWM) ISA总线 死区 

分 类 号：TN492[电子电信—微电子学与固体电子学]