一种ECL超高速D触发器的设计与制作  

A Very High Speed ECL D Type Flip Flop

作　　者：熊杰[1] 蒋宗树[1] 

机构地区：[1]电子工业部第24研究所

出　　处：《微电子学》1997年第1期64-67,共4页Microelectronics

摘　　要：介绍了一种ＥＣＬ超高速Ｄ触发器的电路设计、版图设计及工艺制作。研制中成功地解决了高速度与低功耗的矛盾。电路的工作频率典型值为８５０ＭＨｚ，最高可达９００ＭＨｚ以上，功耗电流典型值为３ｍＡ。A very high speed ECL D flip flop is presented.Its circuit and layout design is described,along with its fabrication process.The conflict between high speed and low power was successfully solved in the development.A typical operating frequency of 850 MHz and typical power consumption of 3 mA have been achieved for the fabricated device.

关 键 词：数字集成电路 ECL电路 D触发器 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]