基于Verilog的随机时钟误差测试平台设计  

Design of random clock error test bench in verilog

作　　者：刘杰[1] 姚素英[1] 史再峰[1] 解晓东[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《吉林大学学报（工学版）》2007年第3期667-671,共5页Journal of Jilin University:Engineering and Technology Edition

基　　金：天津市科委科技重点攻关基金项目(043184511)

摘　　要：结合视频模式识别模块的仿真验证,介绍了一种基于Verilog的随机时钟误差测试平台的设计方法。利用Verilog提供的随机数生成函数,并对其加以改进,生成一组近似高斯分布的随机向量,仿效输入信号的真实行为对模块进行仿真。实验结果表明:该方法较好地验证了时钟抖动及信号间随机相位偏差对设计的影响,可用于一些需要进行随机测试的仿真验证中。A method to design combines the simulating verifica random number generation func a random clock error test bench tion of the video mode detector. Thi in verilog was introduced which s method utilizes and improves the tion provided by verilog to generate a set of random vectors, which approximately obey Gauss distribution. Simulation on the module can be carried out by imitating the real timing of the input signals. Simulation results indicate that the proposed method can effectively verify the impacts of the clock jitter and the random phase skew between signals on the design. The method can be used in other random tests.

关 键 词：电子技术 测试平台 时钟抖动 相位偏差 伪随机测试 

分 类 号：TN407[电子电信—微电子学与固体电子学]