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机构地区:[1]国防科学技术大学计算机学院,长沙410073
出 处:《计算机研究与发展》2007年第4期714-721,共8页Journal of Computer Research and Development
基 金:国家自然科学基金项目(60173040)
摘 要:为了兼顾嵌入式处理器设计中的灵活性与高效性,提出配置流驱动计算体系结构.在体系结构设计中将软/硬件界面下移,使功能单元之间的互连网络对编译器可见,并由编译器来完成传输路由,从而支持复杂但更为高效的互连网络.在该体系结构指导下,提出一种支持段式可重构互连网络的专用指令集处理器(ASIP)设计方法.该方法应用到密码领域的3类ASIP设计中表明,与简单总线互连相比,在不影响性能的前提下,可平均节约53%的互连功耗和38.7%的总线数量,从而达到减少总线数量、降低互连功耗的目的.Efficiency and flexibility are crucial features of processors in embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. And the flexibility allows design modifications in order to respond to different applications. In this paper, the configuration stream driven computing architecture (CSDCA) is proposed, which is both flexible and application specific hardware solution for implementation of embedded processors. Different from the traditional very long instruction word (VLIW) architecture or the transport triggered architecture (TTA), in the CSDCA, not only the responsibility of controlling the data transports is moved from the hardware to the compiler, but also the interconnect network between function units is visible to the compiler. So the routing can be performed by the compiler and the architecture can support the efficiency but complex interconnections to achieve low area overhead with low power dissipation. Directed by the CSDCA, an efficient design method for hardware implementation of application specific instruction- set (ASIP) processors is presented, which supports the reconfigurable segmented-bus networks. Experiment results with several practical applications show that the segmented-bus network can save 53 % in power consumption and 38.7 % in bus numbers, while maintaining the same speed compared with the simple-bus network.
关 键 词:配置流驱动计算体系结构 传输触发体系结构 专用指令集处理器 嵌入式处理器
分 类 号:TP303[自动化与计算机技术—计算机系统结构]
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