45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗  

Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology

作　　者：杨松[1] 王宏[1] 杨志家[1] 

机构地区：[1]中国科学院沈阳自动化研究所

出　　处：《Journal of Semiconductors》2007年第5期745-749,共5页半导体学报（英文版）

摘　　要：提出了一种在45nm体硅工艺下使用双-栅氧化层厚度来降低整体泄漏功耗的方法.所提方法具有不增加面积和延时、改善静态噪声边界、对SRAM设计流程的改动很小等优点.提出了三种新型的SRAM单元结构,并且使用这些单元设计了一个32kb的SRAM,仿真结果表明,整体泄漏功耗可以降低50%以上.This paper presents a method based on dual-gate-oxide-thickness assignment to reduce the total leakage power dissipation of SRAM in 45nm bulk technology. The proposed technique incurs neither area nor delay overhead and can improve the static noise margin. In addition,it results in a slight change in the SRAM design flow. Three novel SRAM cell configurations are proposed. Simulation results demonstrate that this technique can reduce the total leakage power dissipation of 32kb of SRAM with these configurations by more than 50%.

关 键 词：栅极泄漏电流 SRAM 栅氧化层厚度 静态噪声边界 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]