低硬件成本的高性能Hash算法加速器VLSI设计  

A High-performance and Low-cost VLSI Implementation of the SHA-1 Hash Function

作　　者：顾叶华[1] 曾晓洋[1] 韩军[1] 张章[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《小型微型计算机系统》2007年第5期940-943,共4页Journal of Chinese Computer Systems

基　　金：国家自然科学基金项目(90407002和60576024)资助;上海市科委AM基金项目(0502)资助

摘　　要：本文基于安全Hash算法(SHA-1),提出了一种结构优化的SHA-1硬件加速器.本设计通过改进数据通路,加快了运算单元的速度;同时,采用动态操作数生成的方法,节约了硬件资源.设计采用SMIC0.25μm CMOS工艺综合,其核心电路(core)等效门为16.8k;在86MHz的工作频率下,其数据吞吐率达1.07Gbps.分析结果显示,该硬件加速器具备低成本和高性能的特点,适用于PDA、智能手机等面积受限的移动设备,具有良好的应用前景.This paper presents an optimized architecture of a SHA-1 accelerator, based on Security Hash Algorithm. By improving the datapath and adopting the dynamic operand generation technology, the proposed design achieves the goal of high-performance and low-cost. Based on SMIC 0. 25μm standard CMOS technology, the core circuit of this SHA-1 accelerator has about 16.8k gates. Under 86MHz system clock frequency, it achieves a throughput of about 1.07Gbps. The results shows that it is suitable for applications in PDA, mobile telephone, etc. , which demands limited area.

关 键 词：安全Hash算法SHA-1 低成本 VLSI 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构] TN47[自动化与计算机技术—计算机科学与技术]