基于DA算法的二维DCT变换的FPGA实现  

FPGA Implementation of 2D-DCT Based on DA

作　　者：唐赛明[1] 黎福海[1] 

机构地区：[1]湖南大学电气与信息工程学院,湖南长沙410082

出　　处：《仪表技术》2007年第6期30-32,35,共4页Instrumentation Technology

摘　　要：介绍一种基于行列变换快速算法的DCT处理的FPGA实现的方法,阐述了实现这一算法的电路结构。电路中采用基于改进型DA分布算法的乘积累加器和流水线结构,减少了片内资源的占用,提高了速度。给出了VHDL综合后的时序仿真结果,结果显示设计的正确性,满足视频图像压缩需要的实时应用。In this paper, we present a method of FPGA implementation, which based on the algorithm of matrix row-column transposition, and circuit designs in details. In order to reduce resource used in the chip and improve the throughout performance, two technologies of pipeline structure and Multiply-Accumulator based on improved distributed arithmetic/（DA） are employed. In the end, VHDL synthesis results are provided, which show that method meets the real-time application of video and image compression.

关 键 词：DCT变换 分布式算法 FPGA 图像压缩 

分 类 号：TM930[电气工程—电力电子与电力传动]