CMOS单片集成超低压差线性稳压器设计  

Design of a CMOS Monolithic VLDO Voltage Regulator

作　　者：余华[1] 邹雪城[1] 

机构地区：[1]华中科技大学电子与科学技术系

出　　处：《电子器件》2007年第3期859-862,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金资助项目(90207020)

摘　　要：设计了一种具有过热保护、限流保护、快速启动等特性的CMOS单片集成超低压差线性稳压器,对其电路结构及其工作原理进行了分析,给出了主要子模块电路的设计方案,提出了设计方法和设计中所需考虑的问题。该稳压芯片,输入电压范围为2.5～6V,输入输出压差的典型值为0.4mV@1mA和52mV@150mA,电压调整率典型值为0.0126%/V,负载调整率典型值为0.00012%,静态电流的典型值为85μA。This paper presented a monolithic CMOS monolithic very low dropout voltage（VLDO） regulator with functions of thermal protection, internal current limiting and fast transient. The structure and principles were analyzed and sub-block circuits were given. Design methods and issues of the chip were presented too. The regulator has a wide range of power supply from 2. 5 V to 6 V. The Hspice simulation results show that the typical dropout is 0.4 mV@1 mA and 52 mV@150 mA respectively, and the typical voltage line regulation error was 0. 0126%/V. In addition, the typical load regulation error was 0. 000 12% and the typical quiescent current is less than 85 μA.

关 键 词：超低压差 线性稳压器 线性调整 负载调整 低静态电流 

分 类 号：TN432[电子电信—微电子学与固体电子学]