一种用在Σ-Δ ADC中的六阶MASH算法  

A Sixth-order MASH Algorithm used in Σ-Δ ADC

作　　者：谭延军[1] 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2007年第3期10-13,共4页Microprocessors

摘　　要：为了提高SDM ADC的信噪比和降低过采样率,必须采用高阶调制器。通过对单环调制器和MASH调制器性能进行较详细的分析,结合减小芯片面积和器件个数,同时保证较大的动态范围,研究了六阶MASH的不同组合,其中MASH(2-2-2)结构的调制器是最优化的。文章采用单比特量化,利用MATLAB的simulink工具对三级MASH(2-2-2)结构进行了仿真,结果表明该方案提高了系统的整体性能。In order to improve SNR and decrease over sampling of SDM ADC, higher - order modulator must be used. After detailed analysis on the performance of signal cycle modulator and MASH modulator, different combination of six - order MASH, which has smaller chip area and device number and larger dynamic range （ DR）, was investigated. It has been shown that MASH （ 2 - 2 - 2） modulator was the most optimized one. The simulation results using the simulink of MATLAB, in this paper, indicted that single bit quantification and three stages MASH （2 -2 -2） had improves the performance of entire system.

关 键 词：单环调制器 MASH调制器 过采样率 噪声整形 

分 类 号：TN4[电子电信—微电子学与固体电子学]