JTAG软核设计与仿真  

JTAG Soft Core Define and Emulation

作　　者：吕彩霞[1] 李哲英[2] 

机构地区：[1]北京交通大学电子信息工程学院,北京100044 [2]北京联合大学信息学院,北京100101

出　　处：《北京联合大学学报》2007年第2期58-62,共5页Journal of Beijing Union University

基　　金：北京市教委科技强教拔尖人才项目(1110154160)

摘　　要：硬件系统的规模越来越大,复杂度越来越来高,对其进行测试也越来越困难,JTAG边界扫描技术较好地解决了传统测试的不足,边界扫描测试是一种新型的VLSI电路测试及可测试性设计方法。JTAG是符合IEEE规范的测试技术,JTAG的设计实现了测试复杂度的降低,适合进行大规模集成电路的测试。论述边界扫描技术的结构特征及软核设计方法的同时,分析了JTAG电路中数据传输的路径及电路对速度的影响,并以采样指令为例进行了功能仿真。As the scale and complexity of hardware systems increased quickly, it is now more difficult to test them. The JTAG boundary scan technology can well make up the shortcoming of traditional test technology. Boundary-scan technology is a new and effective way of test and design-for-testability for VLSI circuits. JTAG is the test technology of IEEE specification. Its implementation reduces the complexity of the testing and is suitable for VLSI testing. The boundary-scan, the configuration character and soft core design methods are introduced. It also analyzes the route of data transfers and effects on speed in JTAG circuit, and emulated via a sampling instruction.

关 键 词：JTAG 边界扫描 逻辑仿真 大规模集成电路 

分 类 号：TP306[自动化与计算机技术—计算机系统结构]