一种EW接收机信号处理系统的设计与实现方法  

Design and implementation of signal processing system for electronic warfare receiver

作　　者：王晓君[1] 陈禾[1] 罗跃东[1] 

机构地区：[1]北京理工大学信息科学技术学院

出　　处：《河北科技大学学报》2007年第2期142-146,共5页Journal of Hebei University of Science and Technology

摘　　要：设计了一种基于FFT／IFFT、全FPGA实现、环形结构的电子战数字接收机信号处理系统，它由4片FPGA分别实现高速数据传输接口、FFT／IFFT运算及信号的时／频域检测。该系统可完成1～1024K点的FFT运算及1～64K点的IFFT运算，可检测出4个同时到达的脉冲雷达信号的脉冲描述字参数。系统中FPGA以分布式、多总线、并行、流水方式工作，当采用256K点的FFT变换、32K点的IFFT变换时，检测出4个信号的典型用时约20ms。A signal processing system of EW digital receiver is introduced. It is based on FFT/IFFT algorithm, and realized completely by FPGA and constructed annularly. The four FPGAs in the system implement respectively high-speed data transmission interface, FFT/IFFT operation and signal detection in time/frequency domain. The system can do 1～1 024 K points FFT operation, 1～64 K points IFFT operation and can detect the parameters of pulse description word for 4 simultaneous-arrlval signals at most. The FPGAs in the system run with distributed, multi-bus, parallel and pipeline mode and they need only a- bout 20 ms to detect 4 signals while 256 K-point FFT and 32 K-point IFFT are adopted.

关 键 词：电子战 数字接收机 信号处理系统 FPGA FFT 

分 类 号：TN911.72[电子电信—通信与信息系统]