基于FPGA的Turbo译码交织器设计  

Design of Turbo Decoder Interleaver Based on FPGA

作　　者：赵旦峰[1] 雷李云[1] 罗清华 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001

出　　处：《信息与电子工程》2007年第3期186-189,共4页information and electronic engineering

基　　金：黑龙江省自然科学基金资助项目(F200503)

摘　　要：介绍了一种Turbo译码交织器的现场可编程门阵列(Field Programmable Gate Array,FPGA)硬件实现方案,将交织算法的软件编程和FPGA内部的硬件存储块相结合,有效地降低了译码器的硬件实现复杂度,减小了译码延时,并且给出了具体的译码器内交织器FPGA实现原理框图。This paper has introduced a FPGA implementation scheme of interleaver of turbo decoder. This scheme, which combines software programme of interleaver algorithm with the block memory of FPGA, effectively reduces the implementation complexity of the decoder, and the delay of decoding, and shows a detailed FPGA implementation schematic diagram.

关 键 词：TURBO码 交织器 FPGA 译码 延时 

分 类 号：TN764[电子电信—电路与系统]