适用于空间环境下的FPGA容错与重构体系  

Architecture for Fault-tolerance and Reconfiguration of FPGA in Aerospace

作　　者：徐斌[1] 王贞松[1] 陈冰冰[1] 章立生[1] 

机构地区：[1]中国科学院计算技术研究所

出　　处：《计算机工程》2007年第3期231-233,共3页Computer Engineering

基　　金：国家"973"计划基金资助项目(2004CB318202);中国科学院计算所知识创新科研基金资助项目(20056210);国家自然科学基金资助项目(60303017)

摘　　要：FPGA极大地提高了电子系统设计的灵活性和通用性,被广泛地应用在各个领域。在空间环境中,FPGA容易受到SEU的影响而导致内部逻辑的紊乱,系统重构与故障恢复也比较困难。该文提出了一种在星载环境下,使用CPLD对FPGA进行基于错误诊断的容错体系结构设计,兼顾到了系统重构与故障恢复,在实验中取得了较好的效果。FPGA greatly improves the flexibility and universality of electronic system, and is widely used in various fields. However FPGA is sensitive to SEU in aerospace which leading to the destruction of internal user logic. Updating and fault-recovery of system-level are also quite difficult. Based upon this, this paper presents an architecture that detects and corrects the fault of FPGA based upon error diagnosis with a CPLD in aerospace. Meantime, this architecture can also implement reconfiguration and fault-recovery at system-level.

关 键 词：空间环境 SEU FPGA容错 CPLD 重构 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]