一种高性能子字并行乘法器的设计与实现  

Design and implementation of high performance subword parallel multiplier

作　　者：黄立波[1] 岳虹[1] 陆洪毅[1] 戴葵[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机工程与应用》2007年第20期104-106,131,共4页Computer Engineering and Applications

基　　金：国家自然科学基金(the National Natural Science Foundation of China under Grant No.90407022)

摘　　要：提出了一种支持子字并行的乘法器体系结构,并完成了其VLSI设计与实现。该乘法器在16bit阵列子字并行结构的基础上,扩展了有符号与无符号之间的混合操作,采用多周期合并技术,实现了32bit宽度的子字并行,并支持子字模式的乘累加,同时采用流水线设计技术,能够在单周期内完成4个8×8、2个16×16或1个32×16的有符号/无符号乘法操作。0.18μm的标准单元库的实现表明该乘法器既能减小面积又能提高主频,是硬件消耗和运算性能的较好折衷,非常适用于多媒体微处理器的设计。This paper proposes a multiplier architecture capable of supporting subword parallelism,and has completed its VLSI design and implementation using 0.18 μm standard cell process.Based on the 16 bit array sub-word parallel architecture,this multiplier extends signed and unsigned hybrid operations,and uses multi-cycle combination technique to realize 32 bit sub-word parallel operations.In addition,it also supports sub-word multiply accumulate operations.With pipelined operation style,it can per- form one 32×16,two 16×16,and four 8×8 bit signed/unsigned multiplications in single cycle respectively.The implementation resuits show that the proposed sub-word parallel multiplier can reduce the area and improve the frequency ,which is a good com- promise of hardware consumption and performance.h is well suitable for multimedia microprocessor design.

关 键 词：子字并行 乘法器 多媒体 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]