基于FPGA的浮点FIR滤波器的设计与实现  

Design and FPGA Implementation of FIR Filter Using Floating-Point

作　　者：朱蕾[1] 王斌[1] 

机构地区：[1]解放军信息工程大学信息工程学院,河南郑州450002

出　　处：《微电子学与计算机》2007年第7期59-62,共4页Microelectronics & Computer

摘　　要：针对短波宽带接收机系统中信号动态范围大的特点,自定义了24位的浮点格式,并采用流水线技术设计了该格式浮点数的加法和乘法运算单元。在分析了各种FIR滤波器优缺点的基础上,结合FPGA的特点给出了转置型FIR校正滤波器设计方案。最后,以数据率为2.5MS/S的宽带信号为输入,Altera公司的EP2S60F672C5芯片为硬件平台仿真实现了10通道短波宽带接收机的250阶FIR校正滤波器,最高运行速率达到130MHz以上。To satisfy the large dynamic range requirement of shortwave wide band receiver, a floating-point format is defined. Adder and multiplier units for this format numbers are designed using pipelining technique on FPGA. On the analysis of several kinds of FIR filter architectures, according to FPGA features, a transpose-form correcting filter is designed. Finally, ten channels 250 taps FIR correcting filters of shortwave wideband receiver using a wide band signal with a data rate of 2.5MS/S as its input are realized on Altera EP2S60F672CS, with the max frequency reaches 130MHz.

关 键 词：浮点运算 FIR校正滤波器 流水线技术 短波宽带信号 

分 类 号：TN911.72[电子电信—通信与信息系统]