基于CVI+FPGA的声纳目标回波模拟器研制  

Design of Sonar Target Echo Simulator Based on CVI+FPGA

作　　者：赵红军[1] 杨日杰[1] 

机构地区：[1]海军航空工程学院信息融合研究所,烟台264001

出　　处：《计算机工程》2007年第14期227-229,232,共4页Computer Engineering

基　　金：国家自然科学基金资助项目(60572161)

摘　　要：在对声纳目标回波模拟器的数学模型、目标回波模型和混响模型研究的基础上,研制了一种基于CVI+FPGA的声纳目标回波模拟器,该模拟器能够产生主/被动声纳测试、定检所需的主/被动声纳回波信号。目标回波信号包括主动声纳、目标发射噪声、海杂波等信号,并以声信号的形式输出。通过性能测试及与实际声纳系统联试,证明该模拟器达到了设计功能和性能指标要求,介绍了声纳目标回波模拟器的数学模型、系统硬件和软件的实现方法。A simulator of sonar target echo has been designed on the base of its mathematical model, target echo model and reverberation model. It can generate active or passive sonar echo signal including passive or active sonar signal, target radiated noise, sea clutter and reverberation signal for passive or active sonar test and inspection. Output form of the sonar target echo simulator is acoustic signal. It has been proved that the simulator meets the standard of the design function and performance by way of performance test and test with practical sonar system. The paper introduces the mathematical model of sonar target echo simulator, and it emphasizes the way to achieve the simulator system＇s hardware and software.

关 键 词：声纳 模拟器 目标回波 数学模型 CVI FPGA 

分 类 号：TN912.34[电子电信—通信与信息系统]