一种用于高速锁相环的双斜鉴频鉴相器设计  

A Fast Locking PLL with Dual-Slope Phase Frequency Detector

作　　者：丁浩[1] DING Hao （China Electronics Technology Group Corporation No.38 Research Institute,Hefei 230031,China）

机构地区：[1]中国电子科技集团公司第38研究所,安徽合肥230031

出　　处：《电脑知识与技术》2007年第6期1328-1328,1356,共2页Computer Knowledge and Technology

摘　　要：文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计。这种结构是基于两个调谐电路：细调电路和粗调电路。细调电路用来完成精确调制，粗调电路用来加快锁定速度。用MENTOR GRAPHICS-ADMS对电路进行仿真。结果表明所提出的结构比普通型锁相环的锁定时间减少了50％以上。A fast locking phase-locked loops （PLL） with a dual-slope phase frequency detector circuit is presented.The proposed topolopy is based on two tuning circuits： a fine-tuning circuit and a coarse-tuning circuit. A fine-tuning circuit is used for complete fine. adjustments, a coarse-tuning circuit is used for fast convergence.MENTOR GRAPHICS-ADMS simulation shows that the lock time of the prosed PLL can be reduced over 50% in comparison to the conventional PLL.

关 键 词：锁相环 双斜鉴频鉴相器 电荷泵 

分 类 号：TN492[电子电信—微电子学与固体电子学]