基于0.18μm CMOS工艺的2.4/5.2GHz双频段LNA的设计  

Design of a 2.4/5.2 GHz Dual-Band Low-Noise Amplifier in 0.18 μm CMOS Progress

作　　者：景一欧[1] 李勇[1] 赖宗声[1] 孙玲[2] 景为平[2] 

机构地区：[1]华东师范大学信息学院电子系,上海200062 [2]南通大学江苏省专用集成电路设计重点实验室,江苏南通226007

出　　处：《电子器件》2007年第4期1144-1147,共4页Chinese Journal of Electron Devices

基　　金：上海市科委项目(06SA14);江苏省专用集成电路设计重点实验室开放课题(JSIICK0601);江苏省高科技研究(工业部分)资助(BG2005022)

摘　　要：采用0.18μm CMOS工艺,实现了双频段低噪声放大器设计.通过射频选择开关,电路可以分别工作在无线局域网标准802.11g规定的2.4 GHz和802.11a规定的5.2 GHz频段.该低噪声放大器为共源共栅结构,设计中采用了噪声阻抗和输入阻抗同时匹配的噪声优化技术.电路仿真结果表明:在2.4 GHz频段电路线性增益为15.4 dB,噪声系数为2.3 dB,1 dB压缩点为-12.5 dBm,IIP3为-4.7 dBm;5.2 GHz频段线性增益为12.5 dB,噪声系数为2.9 dB,1 dB压缩点为-11.3dBm,IIP3为-5.5 dBm.Based on 0. 18μm CMOS technology, a dual-band low-noise amplifier for WLAN application was implemented. By switching the power source and the output unit, the narrow-band gain and impedance matching were achieved at the 2.4 GHz and 5.2 GHz frequency bands. This circuit adopted traditional cascode structure and a simultaneously input and noise impedance matching technique was used for noise optimization at the same time. The simulation results showed that the LNA exhibited a linear gain of 15.4 dB at 2.4 GHz and 12.5 dB at 5. 2 GHz, noise figure of 2. 3/2. 9 dB, 1 dB compress point of -12. 5/-11. 2 dBm and IIP3 of -4. 7/-5. 5 dBm separately.

关 键 词：低噪声放大器 共源共栅结构 双频段 射频开关 阻抗匹配 

分 类 号：TN433[电子电信—微电子学与固体电子学]