一种改进的片内ESD保护电路仿真设计方法  

A Modified Simulation Design Methodology for On-Chip ESD Protection Circuit

作　　者：朱志炜[1] 郝跃[1] 马晓华[1] 

机构地区：[1]西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《电子器件》2007年第4期1159-1163,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金支持研究(60376024)

摘　　要：对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.A modified method gotten from the present simulation design method is reported for on-chip ESD protection circuits in deep submicron technology. A new stimulus generation circuit is introduced to simplifies the simulation model, and the new ESD failure threshold is appended which takes the oxide breakdown into account. In order to describe the non-local transport of the MOSFET in deep submicron, the energy balance equation is adopted, and some modification is also made on the impact ionization model. Then, an empirical model of the electron energy relaxation time varied with the electron energy is obtained from Monte-Carlo （MC） simulation. Finally, an ESD protection circuit was designed and verified by this method. The test results show that ESD protection circuit operates well under the demanded condition.

关 键 词：静电放电 片内ESD保护电路 混合模式仿真 能量驰豫时间 非本地输运 

分 类 号：TN432[电子电信—微电子学与固体电子学]