基于CDCM7005的时钟设计及其在数字中频系统中的应用  

Low Jitter Clock Module Based on CDCM7005 and Their Applications in Digital Intermediate Frequency System

作　　者：李骏[1] 张福洪[1] 李义慧[2] 

机构地区：[1]杭州电子科技大学通信工程学院,杭州310018 [2]东南大学射频和光电集成电路研究所,南京210096

出　　处：《电子器件》2007年第4期1365-1368,共4页Chinese Journal of Electron Devices

摘　　要：高速ADC、DAC对时钟质量的要求越来越高.对此介绍了一种基于时钟同步器与抖动清除器CDCM7005的低抖动时钟设计.并分析了时钟抖动对信噪比的影响及抖动的计算,介绍了在WCDMA数字中频系统中CDCM7005的具体设计应用,引入了SignalTap这种新的测试方法,最后测试了时钟性能,计算了时钟相位噪声、抖动值和ADC的信噪比,整体指标达到设计要求.The requirement of clock＇s quality in ADC, DAC system increased quickly. A new low jitter method which based on Clock Synchronizer and Jitter Cleaner CDCM7005 was proposed. We analysed the relationship between clock jitter and SNR, and introduced the calculation of jitter. The application of CDCM7005 in WCDMA digital Intermediate Frequency system was presented . And a new testing method which used SignalTap was introduced. At last, we tested the performance of clock, calculated the jitter of cldck,phase noise and ADC＇s SNR. The quality of clock met the system requirements well.

关 键 词：数字中频 时钟抖动 CDCM7005 相位噪声 信噪比 SignalTap 

分 类 号：TN43[电子电信—微电子学与固体电子学]