一种高速Viterbi译码器幸存路径管理模块的改进结构  

Optimized Architecture of Survivor Path Management Unit of High-Speed Viterbi Decoder

作　　者：陈亦灏[1] 李成诗[1] 李小进[1] 赖宗声[1] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062

出　　处：《微电子学与计算机》2007年第8期99-101,105,共4页Microelectronics & Computer

基　　金：上海市AM基金(AM0508;AM0513;AM0403);上海市经委信息委基金(04-联专-001);上海市科委基金(047062023)

摘　　要：针对高速Viterbi译码器的高速,低延迟,低电路复杂度的要求,在分段执行的Hybrid Trace Forward方法的基础上,提出了一种新的幸存路径管理模块(SMU)结构—固定段长的结构。对于(m,n,k)的Viterbi译码器,约束长度为k,则固定段长为k-1,既节省了存储空间,又消除了回溯过程,从而降低了延迟时间和电路复杂度。文中设计了一个(2,1,7)Viterbi译码器的SMU模块,采用固定长度为6的结构。相比于传统的分段执行的Hybrid Trace Forward结构,译码延迟减小了17%,输出数据间隔减小了33%,并且省去了存储器的使用。This paper presents a novel architecture of survivor path management unit of high-speed Viterbi decoder, which is based on the subsection of Hybrid Trace Forward architecture. The length of each block is fixed in this architecture. For a （m, n, k） Viterbi decoder, the length is set as k-1, and the new architecture abandons the RAM and the process of trace back, so as to decrease the latency and complication. We design a SMU module of （2, 1,7） Viterbi decoder and set the length of block 6. Compared with the subsection of Hybrid Trace Forward architecture, the latency decreases 17%, the interval of output data decreases 33%, and the RAMs are abandoned.

关 键 词：混合式前向追踪 延迟时间 固定段长 回溯 

分 类 号：TN4[电子电信—微电子学与固体电子学]