一种降低寄生电容影响的64×4红外焦平面读出电路  

A 64×4 IRFPA Readout IC with Low Parasitic Capacitance Effect

作　　者：唐矩[1] 鲁文高[1] 陈中建[1] 吉利久[1] 张兴[1] 

机构地区：[1]北京大学信息科学学院微电子系,北京100871

出　　处：《红外》2007年第8期1-5,共5页Infrared

基　　金：云南省省院省校科技合作计划项目(2006YX28)

摘　　要：本文提出了一种64×4扫描型红外焦平面读出电路。电路采用0.5μm标准CMOS工艺。工作电压为5V。本设计在列读出级采用了降低寄生电容影响的设计,以降低电路输出相对无寄生电容设计输出值的偏差,提高各通道的一致性。在对具有4级TDI、微扫描步长为探测器中心间距1/3的读出电路列暂存级进行的仿真中,相对于改进前的普通电路结构,本文提出的新型电路结构与设计理想值之间的偏差降为原来的10%。In this paper, a novel 64×4 scanning IRFPA （Infrared Focal Plane Array） readout integrated circuit is proposed. The circuit is made by a standard 0.5μm CMOS process and operates at the voltage of 5V. In order to reduce the output deviation due to the parasitic capacitance and improve the uniformity of signal channels, a low parasitic capacitance effect design is used in the column readout stage of the circuit. A column readout stage which has a four-stage TDI （Time Delay Integration） and a scanning step length of one-third of the detector pitch is simulated. The simulation result has shown that the output deviation of this novel circuit structure is reduced by a factor of 10% compared with that of the original column readout stage.

关 键 词：读出电路 寄生电容 列读出级 

分 类 号：TN215[电子电信—物理电子学]